+[[!format verilog """
+module vc_Mux2 #( parameter W = 1 )
+(
+ input [W-1:0] in0, in1,
+ input sel,
+ output reg [W-1:0] out
+);
+
+ always @(*)
+ begin
+ case ( sel )
+ 1'd0 : out = in0;
+ 1'd1 : out = in1;
+ default : out = {W{1'bx}};
+ endcase
+ end
+
+endmodule
+"""]]